{"id":408,"date":"2023-06-28T11:53:55","date_gmt":"2023-06-28T11:53:55","guid":{"rendered":"http:\/\/localhost\/embeddedwala\/?p=408"},"modified":"2023-07-27T04:12:56","modified_gmt":"2023-07-27T04:12:56","slug":"what-is-dma","status":"publish","type":"post","link":"https:\/\/embeddedwala.com\/beta\/blogs\/digital-communication\/what-is-dma\/","title":{"rendered":"What is DMA?"},"content":{"rendered":"\t\t
\n\t\t\t\t\t\t\t\t\t
\n\t\t\t\t\t\t
\n\t\t\t\t\t
\n\t\t\t
\n\t\t\t\t\t\t\t\t
\n\t\t\t\t\t\t
\n\t\t\t\t\t
\n\t\t\t
\n\t\t\t\t\t\t\t\t
\n\t\t\t\t
\n\t\t\t\t\t\t\t

CPU is an essential part of an Embedded System that manages all the arithmetic, logic, control, and I\/O operations. The main components of the CPU are Control Unit (CU), Arithmetic & Logic Unit (ALU), and the registers.\u00a0\u00a0<\/span>\u00a0<\/p>

\"\"\u00a0CU<\/strong>\u00a0manages the\u00a0ALU<\/strong>\u00a0and memory communication for executing or storing the instructions. It includes the fetching unit for fetching the instructions. On the other hand, the ALU unit manages all the arithmetic and logical operations. During the data transmission between memory and the peripherals, a delay will add if the CPU is engaged to accomplish some other task. Therefore, the system performance gets degraded.\u00a0\u00a0\u00a0<\/span><\/p>

\"\"<\/p>

As shown above, the CPU and multiple peripherals connect with a\u00a0bus matrix<\/strong>. The in-hardware CPU uses the bus interconnected (further expands to the data, control and address bus) to load the data from one of the peripherals and then store it in memory or vice-versa. As a Use Case scenario, the UART is one of the peripherals and wants to transfer the data from its data register to the memory. Therefore, the CPU needs to be programmed to do this transfer of data from the UART Data Register to the memory.\u00a0\u00a0<\/span>\u00a0<\/p>

\"\"<\/p>

The peripherals can only generate the asynchronous events (interrupts) to indicate to the CPU that data is ready but unable to do the bus transactions. Therefore to offload the CPU, a kind of master is essential who can do these transactions without the CPU intervention. The Hardware IP that can control the data transfer between the memory and the peripherals without the CPU involvement is known\u00a0Direct Memory Access (DMA) controller<\/strong>. DMA can access the memory and the peripherals directly for doing the bus transactions. However, Load Store instruction execution and other internal circuitry would only be active during the CPU execution. Therefore, Power Consumption will be less with DMA because the CPU can be in sleep mode during the data transmission.\u00a0\u00a0<\/span>\u00a0<\/p>

\"\"<\/p>

A System on Chip (SoC) is an integrated circuit with all the essential elements required for an Embedded System. In an SoC, the\u00a0Advanced Microcontroller Bus Architecture (AMBA)<\/strong>\u00a0is an open standard that is developed by\u00a0ARM<\/strong>. AMBA has a\u00a0master-slave<\/strong>\u00a0type of topology, only the master can initiate the communication. AMBA connects and manages all the components like Memory and Peripherals e.g. UART, CPU and etc. For managing on-chip communication AMBA has three buses as follows,\u00a0Advanced High-Performance Bus (AHB)<\/strong>, the\u00a0Advanced System Bus (ASB)<\/strong>, and the\u00a0Advanced Peripheral Bus (APB)<\/strong>. The AHB facilitates high-frequency and high-performance components. On the other hand, ASB is an alternative to the AHB but with limited features. Whereas, APB is for taking care of the low bandwidth peripherals like GPIOs, Timers, and UART.\u00a0<\/span>\u00a0<\/p>

The master has the privilege to control the bus and there can be multiple masters in an SoC, but a single master would be able to access the bus at a particular time. To resolve the multi-master access request in hardware, an\u00a0arbiter<\/strong>\u00a0is used. When any master wants to control the AHB bus, it sends a request signal to the arbiter and it will provide access if the bus is available at that particular time. If multiple masters send an access request signal simultaneously, then access will be given to the master having higher priority. Therefore, another master request can stop the CPU access to the system bus for a few bus cycles when the CPU and another master are trying to access the same destination simultaneously.\u00a0<\/span>\u00a0<\/p>

The bus matrix provides access from a master to a slave, enabling concurrent access and efficient operation. The description of these masters is as below:<\/span>\u00a0<\/p>

  • I-Bus: Instruction Bus uses by the core for fetching the instruction. The target of this bus is a memory containing code like Flash, Static RAM, and External Memory.\u00a0<\/span>\u00a0<\/li>
  • D-Bus: Data bus uses by the core for literal load and debugs access. The target of this bus is a memory containing code or data like Flash, Static RAM & External Memory.\u00a0\u00a0<\/span>\u00a0<\/li>
  • S-Bus: System Bus is used to access the data in a peripheral or SRAM. It is also able to fetch instructions and is slower than the I & D Bus. It connects with all the slaves except Flash.\u00a0\u00a0\u00a0<\/span>\u00a0<\/li>
  • DMA Memory: It is used by the DMA for transferring the data to\/from memories.\u00a0\u00a0\u00a0<\/span>\u00a0<\/li>
  • DMA Peripheral: This bus is used by the DMA to access AHB peripherals or to perform memory-to-memory transfers. The targets of this bus are the AHB, APB peripherals, and data memories. DMA2 Peripheral is unable to communicate with Memories whereas it’s possible in the case of DMA1. It depends on the system architecture.\u00a0\u00a0\u00a0<\/span>\u00a0<\/li>
  • USB OTG HS Bus: This bus is used by the<\/span>\u00a0USB OTG to load\/store<\/span>\u00a0data in memory.\u00a0\u00a0<\/span>\u00a0<\/li><\/ul>

    Let’s take an example of ARM Cortex M-4 architecture, where the system consists of a 32-bit multilayer AHB bus matrix that interconnects multiple masters and slaves. CPU Instruction, Data, System bus, DMAs, and USB are acting as masters. On the other hand, Flash, SRAM, and all the peripherals connected with AHB & APB buses are working as a slave.\u00a0<\/span>\u00a0<\/p>

    DMA controller supports two transfer modes which are as below:<\/span>\u00a0<\/p>

    1. Burst Transfer<\/span><\/b>\u00a0\u2013 The entire chunk of data is transferred continuously without interruption. The control of the bus is given back to the CPU when the entire chunk of data is transferred. The disadvantage of this transfer is that if the CPU needs any data from memory during this time, it needs to wait until the transf<\/span>er is complete.<\/span>\u00a0<\/span>\u00a0<\/li>
    2. Split cycle transfer<\/span><\/b>\u00a0\u2013 The control of the bus is given back to the CPU periodically. The data transfer doesn\u2019t happen continuously. The advantage is that the CPU doesn\u2019t sit idle for a given amount of time, waiting for data from memory.<\/span>\u00a0<\/span>\u00a0<\/li><\/ol>

      DMA can be configured into 3 Modes:\u00a0<\/span>\u00a0<\/p>