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Overview
In an Embedded System, a Microcontroller or Microprocessor uses the Input/Output pins to interact with the outer world and the other devices. Output pins take the data or information out and input pins to read the data or information. Software on the microprocessor runs at a very high speed than the hardware interactions. A few milliseconds of delay with the hardware could be thousands of instructions for the software. So for optimal hardware and software interaction, there is a mechanism called interrupts.
An interrupt is a hardware signal to the CPU, which can pause the program subroutine execution of the CPU and executes another subroutine called ISR (interrupt subroutine). ISR function call is asynchronous means execution of the function will be dependent upon the Interrupt triggering. The location for this ISR function in most CPUs is given as an entry value as a function pointer in the Interrupt Vector Table.
The CPU gets the indication of an interrupt trigger via the interrupt controller. Interrupt Controller Handles the interrupt hardware lines and translates the query to the CPU using the ISR instruction set. Based on the Instruction branch offset number CPU execute the function inside the interrupt vector table. Some MCU also uses the Interrupt controller for multiplexing the multiple hardware signal to interface with the CPU. Interrupt controller also has multiple fixed and programable configurations depending on the Interrupt Controller IP type e.g. NVIC (Nested Vectored Interrupt Controller), PMC (Programable interrupt Controllers, GIC (Generic Interrupt Controller) etc.
The Interrupt Operation can be divided into three parts as follows :
An Interrupt signal has various triggering and handling configurations. An Interrupt trigger signal can be configured for digital IPs, e.g. SPI, I2C, Hardware timers etc. Interrupt typically have a sequence number and a sequence number is set for a particular IP configuration, each sequence can have ISR Function linked to it. A sequence number is called the sequence in the vector table input. e.g. (I2C0 has an interrupt sequence no 20, 21 and ISR for I2C0 transactions when Hardware Signal triggered for I2C0 TX done will be using the Sequence number 20 ISR and I2C0 RX done will be handled in the Sequence number 21 ISR.) Interrupt configuration in code is done along with the initialization of IPs. It ensures that IP Initialization and interrupt configuration are at the same location, to ease the debugging of the code later.
MCU internally has interrupt lines configured and connected to the IPs e.g. I2C or SPI. IPs directly share a hardware line connected to the interrupt controller. The IPs can be configured to give the trigger signal on the interrupt line, at the end or beginning of a transaction. The interrupt controller raises the system exception to the CPU. Depending upon the exception sequence CPU pauses the current ongoing program execution and starts the execution of the ISR function.
Interrupt gives the possibility of having the two contexts in our program. First is the main sub-routine and the ISR Subroutine. The program stack stores the local variable and return address. When an interrupt is triggered current program stack and the return address information gets stored in a backup register or memory and the program counter (the next address for execution) points to the ISR Function address. In an ARM MCU, we have two stack pointers MSP (Main Stack Pointer) and PSP (Process Stack Pointer). When an interrupt is handled, the PC points to the MSP. The PSP points to the main sub-program.
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